The present invention relates to integrated circuits (IC) and, more particularly to repairing defective memory cells in such ICs.
As ICs continue to include more transistors, static random memory has become increasingly important in storing and retrieving data in digital integrated circuits. Since a static random access memory (referred to as an SRAM) does not require refresh operations, the SRAM is widely used in high speed applications such as high-speed buffer memory and other storage systems.
In recent years, SRAMs have been widely used in mobile phones, computers and other portable devices. In the production process of an SRAM, due to unavoidable environment and process variations, defective memory cells affect the production yield. Therefore, SRAM devices generally include a number of redundant memory cells used to replace defective memory cells in order to improve yield.
These redundant memory cells are designed the same way and operate in the same fashion as the memory cells in a memory device, but increase the silicon area. Under normal operating conditions of a memory device, these redundant memory cells are not accessible (i.e., they cannot be read or written). Their only role is to replace memory cells that do not operate properly. In other words, the redundant memory cells waste silicon real estate if all other memory cells are operating correctly, i.e., when the memory device does not have any defective memory cells.
It has been found that repairing individual memory cells is not economical. Conventionally, when certain memory cells are detected to be not properly accessible or operational (whether in read or write mode), the defective memory cells are replaced by the redundant memory cells that are addressed by the respective row or column addresses of the defective memory cells. For example, when a defect in memory cell A is detected, the row address of defective memory cell A will be recorded. When a read operation is performed on memory cell A, the row address contained in the read command is compared with the recorded row address of the defective memory cell A. If the row address in the read command and the recorded address are the same, the row address contained in the read operation is replaced by the row address of a redundant memory cell. Thus, a read operation to a defective memory cell will result in the read operation of the redundant memory cell having the row address associated with the row address of the defective memory cell. However, this repair scheme will cause non-defective memory cells sharing the same row address to also be replaced, thus, limiting the number of repairable defective memory cells.
Therefore, there is a need for a method and apparatus for effectively repairing defective memory cells.